Massive 300-layer Samsung SSD made possible by new “speed-optimised circuit”

The race to mass manufactured 100+ layer NAND Flash heats up as Samsung announces its sixth generation V-NAND in 256Gb, 3-bit (TLC) chips. This marks the industry’s first attempt to incorporate over 100 layers across a single stack. Aided by a “speed-optimised circuit design,” Samsung plans on stacking multiple 100+ layer chips within high-density SSDs up to 300 layers deep. The company claims to have secured the “industry’s highest performance, power efficiency, and manufacturing productivity” with the latest 3D memory tech, which utilises channel hole etching to increase cell density by 40% over 96-layer fifth generation V-NAND. This is achieved by layering 136 layers of an electrically conducive mold stack, and then piercing holes all the way through with a tiny, fancy holepunch to create uniform charge trap flash (CTF) cells. However, as the cell height increases, error and read latencies also increase. To address this issue as layers increase, Samsung will roll out a new speedy circuit design. This will help achieve faster transfer speeds of below 450μs write and 45μs read. That’s a 10% bump to fifth gen V-NAND and a 15% decrease in power demand.
Syndicated from here: Massive 300-layer Samsung SSD made possible by new “speed-optimised circuit”